The present invention relates to methods and apparatus for managing the effects of a changing latency in the transfer of data between the processors of a multiprocessing system within an integrated circuit.
There continues to be a desire for faster computer processing data throughputs as computer applications involve higher complexity computations, e.g., for real-time, multimedia functionality. Graphics applications are among those that place the highest demands on a processing system because they require such vast numbers of data accesses, data computations, and data manipulations in relatively short periods of time to achieve desirable visual results. These applications require extremely fast processing speeds, such as many thousands of megabits of data per second. While some processing systems employ a single processor to achieve fast processing speeds, others are implemented utilizing multi-processor architectures. In multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.
Large scale integrated circuits are being designed to accommodate an ever increasing number of circuits in order to achieve higher and higher functionality. For example, the digital circuits (or analog circuits) associated with fabricating multiprocessor system are being designed with very high numbers of gates and other functional circuitry to meet processing objectives in the marketplace. As the complexity of integrated circuits (ICs) continue to increase, however, the number of transistors and other components used to implement the circuitry also increases and the probability of a faulty component or circuit occurring in an IC approaches one. The existence of a faulty circuit or component may require that the IC be discarded.
It has been proposed to use redundant circuits on the IC in order to permit replacement of the circuitry containing a faulty component. For example, FIG. 1 illustrates an IC 10 employing digital circuit A, digital circuit B, digital circuit C, and digital circuit D, where one or more of the circuits may be redundant. Thus, even when a fault occurs, the IC 10 may be salvaged by enabling the redundant circuit. This can increase the IC yield and save the IC manufacturer a considerable amount of money. While the redundant circuit(s) may be activated and used in place of the faulty components, the faulty component may be deactivated. Conventional techniques for activating good circuits and deactivating faulty circuits include blowing fuses, such as electrical fuses (e-fuses) and/or laser-trimmed fuses.
The components or circuits of an IC may be faulty due to improper fabrication. For example, an imperfection may have been present on the substrate during fabrication or the fabrication procedure itself may be faulty. Improperly fabricated ICs may be discovered during IC testing, prior to packaging. ICs may also be damaged after the pre-packaging IC testing. The components or circuits of an IC may be faulty due to damage during the packaging of the IC, for example, when the die is cut from the wafer, when the wafer is cleaned, when the die is bonded to the packaging, and so forth. ICs that become faulty due to packaging are usually not discovered until post-packaging testing. If a faulty component is discovered on an IC during pre-packaging IC testing, the faulty component may be deactivated and a redundant circuit activated to take its place through the blowing of certain fuses, preferably, laser fuses since access to the IC is possible because the IC has yet to be packaged. If a faulty component is discovered on an IC after packaging, additional redundant circuits can be activated through the use of electrical fuses (e-fuses), rather than laser fuses, since direct access to the IC is not possible.
Another existing technique for addressing the defective circuit problem may be described in the context of the aforementioned multiprocessor system context, in which a plurality of sub-processors exchange data and operate in parallel to achieve one or more computing goals. By way of example, a multiprocessor system manufacturer may determine that a system in which three sub-processors are operational is desirable and marketable. The manufacturer may establish the fabrication process such that four sub-processors are fabricated on one IC. Thus, even if one sub-processor is defective, three good sub-processors will remain and the IC will not need to be discarded. This approach will result in one of the following scenarios for a given IC: (1) four good sub-processors exist; (2) three good sub-processors exist; or (3) less than three good sub-processors exist. In scenario (3), the IC is discarded. In scenario (2) the defective sub-processor is fully disabled and unused. In scenario (1), one of the four good sub-processors is disabled. Thus, irrespective of which of scenarios (1) and (2) exists, the result is an IC with three working sub-processors—the number that the manufacturer desires and that the software programmer expects. Indeed, software programmers may design programs to operate in the multiprocessor system assuming that three sub-processors are present (no more, no less).
A problem arises, however, when one of the processors is disabled in that the latency pattern as between the available sub-processors is not predictable, which may result in undesirable timing problems. The latency pattern for a particular IC involves the latency of data transfers between respective pairs of sub-processors. The latency depends on the location of the sub-processors on the bus that interconnects them. By way of example, if the interconnecting bus is implemented using a one or more data rings, then the latency of data transfers between pairs of sub-processors will depend where the sub-processors are located along the data ring and in what direction (clockwise or counterclockwise) the data are flowing between them. If the relative locations of the sub-processors on respective ICs are constant, then the manufacturer can specify the latency pattern as between pairs of sub-processors to the software programmers so that they have a predictable latency pattern on which to base their programming. In the context of the defective sub-processor problem discussed above, however, the latency pattern as between respective pairs of sub-processors is not constant because the location of the defective sub-processor is unpredictable. This can result in undesirable timing problems when software is executed on the multiprocessor system.
Thus, another technique to permit disabling of circuitry on an IC (such as the sub-processors of a multiprocessing system) is needed that results in a predictable latency pattern.